B.TECH. IN ELECTRONICS ENGINEERING (VLSI DESIGN AND TECHNOLOGY)corelab
VLSI DESIGN LAB
ECE 2244
Syllabus
- 01Introduction to ASIC Design flow using EDA tool. Verilog modeling of combinational and sequential digital circuits using Verilog.
- 02Synthesize digital circuits targeting suitable library and by setting area and timing constraints.
- 03Analyse the various generated reports such as Area, Power, and Delay for the Synthesized netlist.
- 04Plan the physical design of digital circuits for synthesized netlist using EDA tool and generate GDS-II file.
- 05Mini project using EDA tool.
References
- Charles Roth, Lizy Kurian John, Byeong Kil Lee, “Digital System Design Using Verilog”, Cengage Learning 2015.
- Samir Palnitkar, “Verilog HDL: A Guide to Digital Design and Synthesis”, Prentice Hall Professional, 2003.
- Digital Lab Manual, Revision 2.0, University Support Team, Cadence, Bengaluru, 2017.
- Cadence PVS User Guide, 2023.
- Proakis J. G, Manolakis D. G. Mimitris D., “Introduction to Digital Signal Processing” Prentice Hall, India, 2007.
- Oppenheim A.V, Schafer R. W, “Discrete Time Signal Processing”, Pearson Education, 2004.
- Ifeachar, Jervis, “Digital Signal Processing - A Practical approach”, Pearson Education, Asia, 2003.
- Rabiner L. R, Gold D. J, “Theory and applications of digital signal processing”, Prentice Hall, India, 1998.
- Sanjit Mitra K, “Digital Signal Processing - A computer based approach”, TMH, 2007.
Credits Structure
0Lecture
0Tutorial
3Practical
1Total